Nov 23, 2020 · In this work we report on low temperature (LT) epitaxy (below 500℃) of Si:P layers with extremely low as-grown layer resistivity. Optimal growth conditions at 400℃ led to a layer resistivity of 0.2 mOhm.cm and an active dopant concentration of ~1.15 × 10 21 cm -3 .

The present study examined the effects of three main epitaxy steps (ex-situ cleaning, in-situ bake and the wafer loading environment) upon the quality of Si-based epitaxial films obtained via reduced pressure chemical vapor deposition (RPCVD).

Mar 15, 2022 · 550 °C epitaxy of tensile SiP. with disilane and phosphine. Various strategies evaluated to obtain low resistivities and high [P]subst. High phosphine to disilane mass-flow, low H2 carrier flow and high pressure.

Abstract: This work presents an integrated process to grow epitaxial Si film on NMOS fin S/D (source/drain) area. The Si epitaxy growth behavior has been compared between pure Si epitaxy (Si epitaxy without in-situ P doping) and SiP epitaxy (Si epitaxy with in-situ P doping).

May 25, 2023 · We have developed a low temperature process for tensile-SiP SEG that would be of use for advanced technological nodes devices such as finFETs or stacked nanowires or for monolithic 3D...

Jan 29, 2024 · We investigate Si epitaxy using 3D reactor scale computational fluid dynamics simulations coupled with surface chemistry models for the growth of pure silicon and phosphorus-doped silicon (Si:P) films. We focus on low temperature Si and Si:P processes using dichlorosilane (DCS) and phosphine.

Sep 30, 2022 · We demonstrate the feasibility of selectively growing highly doped and tensile-strained Si:P layers at temperatures 500°C or less on each side of advanced n-type MOS devices.

Mar 15, 2013 · In this paper, the faceted growth of high Phosphorous doped Silicon epitaxy using various process schemes is explored.

Feb 14, 2025 · The upcoming generations of DRAM series requires us to narrow the bit contact (BC) CD down to ~ 10 nm and further decrease the BC resistance. This requires the use of a highly doped epitaxial plug to obtain low resistance BC. In this paper, we study the growth mechanisms and physics of SiP epitaxy.

High strain in-situ phosphorus doped silicon (called HS-Si:P) epitaxy in the source/drain (S/D) areas has been adopted for nMOS transistors for 14nm node and beyond, which can boost nMOS drive current by applying tensile strain on device channel and lower contact resistivity.