IBM POWER5+ 8-way MCM side view. The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller.

The ICs that make up the MCM package may be: ICs that can perform most, if not all of the functions of a component of a computer, such as the CPU. Examples of this include implementations of IBM's POWER5 and Intel's Core 2 Quad. Multiple copies of the same IC are used to build the final product.

On a four-core POWER5+ processor-based system, the OS discovers the available processors as an eight-core system. To achieve a higher performance level, simultaneous multithreading is also applicable in Micro-PartitioningTM, capped or uncapped, and dedicated partition environments.

IBM’s POWER5 Micro Processor Design and Methodology Microprocessor Design Optimization Focus Areas §Memory latency 4 Increased processor speeds make memory appear further away 4 Longer stalls possible §Branch processing 4 Mispredict more costly as pipeline depth increases resulting in stalls and wasted power

Feb 18, 2014 · IBM POWER5+ QCM – 4 dies, 8 cores, and 72MB of L3 Cache. When the POWER5 processor was released in 2004 it was made in two versions, a DCM (Dual Chip Module) containing a POWER5 die and its 36MB L3 cache die, as well as a MCM containing 4 POWER5 die and 4 L3 cache dies totaling 144MB.

Aug 1, 2005 · With a key goal of maintaining both binary and structural compatibility with POWER4™ systems, the POWER5 microprocessor allows system scalability to 64 physical processors. A POWER5 system...

With a key goal of maintaining both binary and structural compatibility with POWER4e systems, the POWER5 microprocessor allows system scalability to 64 physical processors. A POWER5 system allows both single-threaded and multithreaded execution modes.

Possible configurations DCM (Dual Chip Module) One POWER5 chip, one L3 chip MCM (Multi Chip Module) Four POWER5 chips, four L3 chips Communication is handled by a Fabric Bus Controller (FBC) “distributed switch” Typical Configurations 2 MCMs to form a “book” 16 way symmetric multi-processor (appears as 32 way) DCM books also used Fabric ...

Nov 18, 2003 · Power5, which will debut in 2004, will be a dual-core processor with a shared L2 cache memory and external L3 caches integrated on a multi-chip module (MCM). Power5-based systems will be four times as fast as IBM's current Power4-based p690.

To conserve power, the POWER5 chip implements dynamic power management that allows reduced power consumption without affecting performance. This paper describes the implementation of the IBM POWER5™ chip, a two-way simultaneous multithreaded dual-core chip and systems based on it.