Abstract: This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source.

In a DLL-based clock multiplier, the delay of a voltage-controlled delay line (VCDL) is locked to the reference period [1]. Multiple delayed versions of the reference clock from the VCDL are then combined to produce the final clock signal, as shown in Fig. 1(a). The delayed reference is discarded at the end of the VCDL, so the phase realignment is

loops (DLLs) can be considered as feedback circuits that phase lock an output to an input without the use of an oscillator. In some applications, DLLs are neces-sary or preferable over phase-locked loops (PLLs), with their advantages including …

• DLLs lock delay of a voltage-controlled delay line (VCDL) • Typically lock the delay to 1 or ½ input clock cycles • If locking to ½ clock cycle the DLL is sensitive to clock duty cycle

We propose a new dual-loop DLL architecture that allows un-limited delay range by using multiple voltage-controlled delay lines (VCDLs). In our architecture, the reference loop gener-ates four evenly spaced clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to gen-erate the output clock in the main loop.

This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches.

The proposed DLL adopts a new voltage-controlled delay line (VCDL) structure, which reduces the output phase error down to 2.32%. A simple digital auxiliary pulse width regulator is used to adjust the width of output pulse for further reduction of the duty cycle error.

In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock generator circuits. In this work a DLL has been proposed the design uses dynamic phase detector (PD) for phase detection. Voltage controlled delay line (VCDL) of proposed DLL consists of twelve delay elements.

SPICE simulation of the Digital Delay Loop (DDL) that uses the modified version of Voltage-Controlled Delay Line (VCDL). The VCDL gain must be as linear as possible, otherwise the DLL can exhibit second-order locking effects.

False lock or harmonic lock occurs when initial delay is greater then 2 * Tin with PD locking at 0 . Start DLL with reset. On reset, VC forced to 0. Depending on initialization, stuck problem may arise. Delay is at minimum but PD keeps comparing input with current-cycle output not with one-cycle delayed output.