hello , First of all , thank you for the reply.But i am a fresher to the redpitaya Fpga , so if you explain me in detail it would be good for me. i will provide you the documents

Hi @nikhilthapa (Member) Thank you for your reply. It is assumed that the result calculated in the FPGA will be output as an image at the end. It's not a pattern image.

**BEST SOLUTION** This is exactly what I want to do, to limit the skew between SDA and SCL. How can I do that? As I said - use the IOB flip-flops on the pins driving the SDA and S

Aug 22, 2005 · Hi everyone: I just ecounter this error , and don't knwo how to solve it: "FATAL_ERROR:HDLParsers:vhptype.c:174:$Id: vhptype.c,v 1.9 2005/08/22 17:03:34 mikev …

My idea was to connect first the Pmod da2 to the output of the sine generator and then the SPI from the Pmod da2. But I don't know if it is possible. My goal is to be able to read