The STBus is a set of protocols, interfaces, primitives and architectures specifying an interconnect subsystem, versatile in terms of performance, architecture and implementation.

This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently.

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STBus is a communication micro network that ensures high bandwidth and low latency communication. Hence, such a high performance on-chip bus is very complex and highly configurable.

Dedicated for dual HDTV market, the 65 nm chip recently developed by STMicroelectronics integrates one host CPU, two video decoders enabling the decoding of MPEG-2, H264 and VC1 video frames, dedicated micro-processors for audio decoding and many peripherals for internal or external exchanges.

A cache updating method in which data written by the processor or instruction execution part is updated only in the cache, without being reflected directly in memory. The copyback cache supported in STbus has the following three internal states: Invalid state (I), Shared & Unmodified state (SU), Exclusive & Modified state (EM).

This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently.

Oct 25, 2007 · In this work we address this issue of application-specific design of optimal crossbar (using STbus crossbar architecture), satisfying the performance requirements of the application and optimal binding of cores onto the crossbar resources.

The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC. The first section provides a short overview of the VSTNoC.

The SoC interconnect uses two bus protocols: a circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC. The SoC performance verification uses an incremental approach. First, an analytical and statistical method provides early performance figures of the SoC.