The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

Continuous scaling of DRAM chips requires further optimization of saddle fin access transistor performance. This paper presents the TCAD simulation studies of the fin structure effects on the threshold voltage, drivability and subthreshold swing.

May 30, 2023 · Learn how virtual process modeling and optimization techniques can improve the performance of DRAM saddle fins, allowing DRAM manufacturers to enhance device performance without modifying existing device schematics

Abstract: In this study, we investigate a novel design for a saddle-fin-based dynamic random access memory (s-fin DRAM) aimed at mitigating the Rowhammer (RH) effect. This work involves modifying the doping scheme and employing technology computer-aided …

May 15, 2021 · Dynamic random access memory (DRAM) requires periodic refresh operations to retain its data. In practice, DRAM retention times are normally distributed from 64 ms to several seconds.

Jan 1, 2006 · Highly scalable saddle-fin cell transistor (S-Fin) has been successfully developed by combining FinFET with recess channel array transistor (RCAT). The S-Fin is simply integrated by...

Feb 22, 2024 · Saddle Fins were introduced in DRAM devices to increase channel length, prevent short channel effects, and increase data retention times. Critical process equipment settings like etch selectivity or the gas ratio of the etch process, can significantly impact the shape of fabricated saddle fin profiles.

Abstract—Continuous scaling of DRAM chips requires further optimization of saddle fin access transistor performance. This paper presents the TCAD simulation studies of the fin structure effects...

Channel structure evolution of the cell transistor in DRAM: Transmission electron microscope (TEM) images of (i) RCAT, (ii) S-RCAT, and (iii) U-RCAT. (iv) (Middle) Schematic of a saddle-fin transistor with TEM cross-section images of the (left) x- and (right) y-axes of the transistor.

Jun 15, 2023 · To improve the performance of DRAM Saddle Fins, virtual process modeling can be used to study fin structure effects and develop optimal fin structures. Figure 1 (a) displays a single cell of a conventional DRAM that consists of 2 Word Lines (WLs), a Bit Line (BL) and 2 Storage Node Contacts (SNC).