Abstract: Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices.

Dec 22, 2017 · sddc Single Device Data Correction (SDDC) checks and corrects single-bit or multiple-bit (4-bit max.) memory faults that affect an entire single x4 DRAM device.

A similar system from Intel, called Lockstep memory, provides double-device data correction (DDDC) functionality. [4] . Similar systems from Micron, called redundant array of independent NAND (RAIN), and from SandForce, called RAISE level 2, protect data stored on SSDs from any single NAND flash chip failure. [5][6]

confined to a single x4 DRAM chip and detect errors in up to two devices. This capability is known as single-device data correction (SDDC).

The x4 SDDC is an ECC algorithm designed to recover from a single DRAM chip failure of the data signals. x4 SDDC can be configured to correct errors in x4 chips or to correct in x8 chips. Data or data pin errors in the same chip are correctable.

The affected Intel® Xeon® Scalable Processors implemented changes in Single Device Data Correction (SDDC). SDDC is a fundamental Intel RAS (Reliability, Availability, Serviceability) feature available on all platforms.

To fill this void, we present an in-depth data-driven correlative analysis between DRAM errors and server failures, with the primary goal of predicting server failures based on DRAM error characterization and hence enabling proactive reliability maintenance for production data centers.

We propose dual use of on-chip redundancy (DUO), a mech-anism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for …

Feb 1, 2023 · Single device data correction (SDDC) is a main reliability, availability, and serviceability feature of DRAM systems in servers due to the significant hard-failure rate associated with DRAM devices. To correct errors in one DRAM device, error pattern is determined by even parity bits and error location is determined by the error pattern and ...

Sep 19, 2020 · A3: ADDDC enables the platform to dynamically map out the failing DRAM device. After map out occurs, cache lines in the bank/rank are re-arranged from independent mode to virtual lockstep utilizing ADDDC ECC.