Abstract: This paper presents a new voltage controlled delay line (VCDL) for a 30-phase 500MHz DLL. The new VCDL circuit solves the problem of flicker noise caused by the tail current source.

loops (DLLs) can be considered as feedback circuits that phase lock an output to an input without the use of an oscillator. In some applications, DLLs are neces-sary or preferable over phase …

In a DLL-based clock multiplier, the delay of a voltage-controlled delay line (VCDL) is locked to the reference period [1]. Multiple delayed versions of the reference clock from the VCDL are …

We propose a new dual-loop DLL architecture that allows un-limited delay range by using multiple voltage-controlled delay lines (VCDLs). In our architecture, the reference loop gener-ates four …

Jul 12, 2022 · A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable …

False lock or harmonic lock occurs when initial delay is greater then 2 * Tin with PD locking at 0 . Start DLL with reset. On reset, VC forced to 0. Depending on initialization, stuck problem may …

The proposed DLL adopts a new voltage-controlled delay line (VCDL) structure, which reduces the output phase error down to 2.32%. A simple digital auxiliary pulse width regulator is used …

This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty …

In this paper we present design, analysis and implementation of Delay Locked Loop (DLL) based clock generator circuits. In this work a DLL has been proposed the design uses dynamic …

Nov 3, 2017 · In this paper, a low-jitter and wide operating range DLL with eight differential delay stages is proposed for two-segment TDC application, where the VCDL within DLL is fully …