Currently, the most versatile silicon deep trench etches are based upon cyclic etch-deposition processes. At Applied Materials, this process is known as the time multiplex, gas multiplex …

Dec 16, 2017 · There are three important parameters in deep reactive ion etching (DRIE): the etching rate, the sidewall angle, and the sidewall damage. A high etching rate is always a high …

Apr 24, 2007 · This paper presents a method for etching tapered sidewalls in silicon using deep reactive ion etching. The method is based on consecutive switching between anisotropic …

Aug 14, 2012 · We report on a continuous plasma etching process using SF 6 /O 2 /Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The mask diameters of the vias …

Following an overview of the reactive ion etch (RIE) process modeling and its use in simulating deep silicon via etch profile for TSV application, experimental characterization work has been …

Different size vertical trenches with high aspect-ratios of 15:1 ~ 20:1 and smooth sidewalls were achieved using electroplated nickel mask on 100mm SiC wafer, and a trench depth uniformity …

Sep 24, 2007 · Abstract: This work presents a method for etching tapered sidewalls in silicon using deep reactive ion etching. The method is based on consecutive switching between …

Sep 12, 2007 · First a high etch-rate process is performed to form deep silicon vias of required depth followed by photoresist stripping and Piranha clean. The 1st etching step is designed to …

Micro- and nanostructures with a tapered sidewall profile are important for antireflection and light trapping applications in solar cell, light emitting diode, and photodetector/imager. Here, the …

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required …