In order to improve DRAM retention time characteristics, leakage current must be reduced and various solutions are proposed. The major leakage paths in a DRAM cell stem from reverse junction leakage from the storage node, and gate induced drain leakage (GIDL) current.

In this article, leakage current and leakage power analysis for 1T1C DRAM cell structure has been carried out for nanoscale memory devices. This paper investigates the design of a 1T1C DRAM cell at 180nm technology using cadence tool.

Feb 3, 2020 · Cell transistor leakage in DRAM is primarily attributed to “gate induced drain leakage” (GIDL) (Fig.1 (b)), which is a type of leakage caused by a high electric field effect in the drain junction.

Due to the nature of its memory cells, DRAM consumes relatively significant amount of leakage power. In this paper, basic DRAM cells are designed using low power design techniques namely, sleep, stack and sleepy stack for leakage power reduction.

Sep 1, 2009 · We have experimentally analyzed the leakage mechanism by comparing the planar DRAM cell and the recently developed DRAM cell transistors that have deeply recessed channels.

Sep 6, 2022 · Cell transistor leakage in DRAM is mainly due to gate-induced drain leakage current (GIDL) (Figure 1 (b)), which is the leakage current caused by the high electric field effect at the drain junction.

Oct 13, 2017 · Abstract: This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance such as refresh time (tREF).

Feb 1, 2011 · We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method.

In the field of testing more appropriate test algorithms are required to detect weak cells with leakage current sources. The project propose an interleaving test algorithm that takes into account the equal bit-line stress regardless of the cell location.

Feb 27, 2025 · Discover how a dual work-function metal gate (DWMG) structure in DRAM buried word-line (BWL) reduces gate-induced drain leakage (GIDL) while maintaining performance. This innovation is crucial for advancing high-density, low-power DRAM technology.