Jan 26, 2025 · This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping...

We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS.

Sep 5, 2022 · As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance.

Nov 13, 2020 · In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells....

The characterization of data retention weak cells for 30 nm design rule DRAMs with BCAT and RCAT has been investigated. Most weak cells were classified as GIDL leaky cells in both cases. In the case of BCAT, the distance between the word line and the storage node, caused by the process distribution, is the main origin of weak cells.

Nov 13, 2020 · In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures.

This paper introduces an innovative process technology to realize a high-purity and low-resistance cell WL that can solve two critical hurdles simultaneously, enabling the DRAM node of 12 nm and beyond.

Apr 3, 2025 · SF on DRAM cell may will keep over 0.9 for a while on the next three generations, D1a, D1b, and D1c, for 6F 2 BCAT 1T+1C integration. When it comes to DRAM cell scaling, we refer to the cell pitch trends from Samsung, SK Hynix, and Micron DRAM products, including active, WL, and BL pitches.

We discovered that controlling the active dimension and profile is the key factor to improve local variability. This also suggests that a measurement of a threshold voltage in an array of cell transistor could be the effective method to figure out a degree of local variation.

Jan 26, 2025 · This study explains the causes of row hammer in DRAM cell arrays and the pulse operation schemes of single row hammer D1 (SH D1) and D0 (SH D0), while evaluating key parameters in the BCAT structure.