DDR3中的ZQ校准用于输出驱动器和 ODT，每个DRAM的ZQ pin都被连接到外部的±1%精度的240ohm电阻，该电阻是可以在所有的Device之间共享的。

The DDR3 ZQ calibration scheme provides an improvement in controlled impedance values and significantly tighter tolerances when compared with DDR2. The long calibra-tion at initialization enables the DRAM to minimize any process variation present in the driver.

• ZQ calibration—Change the values of on-chip pull-up and pull-down resistors connected to the VCC/2 pins. Unlike all other types of calibration which take place only at the i.MX53 DDR port, ZQ calibration takes place on the DDR device side as well.

Learn about DDR3 ZQ calibration techniques, including merged driver design, ZQCL/ZQCS commands, and calibration timing. Ideal for engineers.

The MIG 7 Series design includes both ZQ Short (ZQCS) and ZQ Long (ZQCL) Calibration commands that adhere to the DDR3 JEDEC Standard. The ZQ Calibration Command is discussed in section 5.5 of JEDEC Specification JESD79-3 DDR3 SDRAM Standard.

This feature is applicable to DDR3 and LPDDR2/LPDDR3. The UDDRC controller uses the ZQ calibration command to calibrate SDRAM RON (Resistor On) and ODT (On-Die Termination) values over PVT (Process, Voltage, Temperature).

The MIG Virtex-6 FPGA DDR3 design includes ZQ Short (ZQCS) and ZQ Long (ZQCL) Calibration commands that adhere to the DDR3 JEDEC Standard. The ZQ Calibration Command is discussed in section 5.5 of JEDEC Spec JESD79-3 DDR3 SDRAM Standard.

For more robust system operation, the DDR3 SDRAM driver design has been enhanced with reduced capacitance, dynamic on-die termination (ODT), and a new calibration

DDR3 adds ZQ calibration function: ZQ is also a new pin, a 240 ohm low-tolerance reference resistor is connected to this pin. This pin uses a command set to automatically verify the on-resistance of the data output driver and the end resistance of the ODT through the on-die calibration engine (ODCE).

May 13, 2019 · 对于DDR3，全功率驱动器的输出阻抗默认为34Ω，通过使能所有7个240Ω引脚获得。 要实现DDR3专有的数据速率，必须特别注意 信号完整性。 最大限度地减少连接存储器控制器和DRAM输出的走线上的任何阻抗不匹配将有助于减少信号上的反射和振铃。 为了帮助减少这些阻抗不连续性，DDR3中引入了精确校准方案。 DDR3中的ZQ校准用于输出驱动器和ODT。 每个DRAM的ZQ球连接到外部精度（±1％）240Ω电阻。 只要控制器不与校准相关的任何时序重 …