
Cray T3E - Wikipedia
The Cray T3E was Cray Research's second-generation massively parallel supercomputer architecture, launched in late November 1995. The first T3E was installed at the Pittsburgh Supercomputing Center in 1996.
Cray T3E Architecture - GeeksforGeeks
Jun 14, 2019 · The CRAY T3E is a scalable shared-memory multiprocessor; The system architecture is designed to tolerate latency and enhance scalability. The T3E system was fully self-hosted and ran the UNICOS/mk distributed operating system. Cray T3E scalability can handle added processors and memory as well as larger I/O and interconnection bandwidths. Broad ...
Cray T3E – Cray-History.net
BERKELEY, CA — Continuing its mission to extend the limits of scientific understanding, Ernest Orlando Lawrence Berkeley National Laboratory (Berkeley Lab) has acquired a Cray T3E, one of the most powerful supercomputers in the world.
This paper describes the interconnection network used in the Cray T3E multiprocessor. The network is a bidirectional 3D torus with fully adaptive routing, optimized virtual chan-nel assignments, integrated barrier synchronization support and considerable fault tolerance.
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The CRAY T3E series
Across a range of configurations from 16 to 2048 proces- sors with corresponding peak perform- ance levels from gigaflops to teraflops, CRAY T3E systems deliver superior scal- able performance and price/performance on technical applications in scientific and engineering R&D and industrial production computing.
CRAY T3E - SpringerLink
This entry describes the hardware and software architecture of the CRAY T3E Massively Parallel Processor (MPP), a landmark supercomputer system that became the first commercially successful MPP, and the first to be used in production data centers around the world.
Cray T3E (T3E) - Cray-Cyber
t3e.cray-cyber.org Times of operation: not yet in operation Machine Type: Cray T3E, 3D Torus interconnect Interconnect Bandwidth: 136 x 500 MB/s = 68 GB/sec Serial number: 6523 Year of introduction: 1996 CPU Type: DEC Alpha EV5 21164 300 MHz / 3.3 nsec Number of processors: 136, air cooled (max configuration) Main memory:
Cray T3E system is widely recognized as the most technically successful highly scalable supercomputer and holds the world record for sustained performance on a full 64-bit application.
Synchronization and communication in the T3E multiprocessor
Sep 1, 1996 · This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the rationale behind changes made for the T3E.
Performance of the CRAY T3E Multiprocessor - IEEE Xplore
The CRAY T3E is a scalable shared-memory multiprocessor based on the DEC Alpha 21164 microprocessor. The system includes a number of architectural features designed to tolerate latency and enhance scalability.
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