Jan 26, 2025 · This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping...

We proposed a multi-gate BCAT structure to minimize gate induced drain leakage and modified the select word-line circuit to operate multi-gate buried cell array transistor by adding only one PMOS.

Nov 13, 2020 · In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells....

Sep 5, 2022 · As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance.

Nov 13, 2020 · In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures.

The local variation of fin height plays a vital role in determining a performance of DRAM and this variation is caused by subtle differences during the process [3]. We discovered that controlling the active dimension and profile is the key factor to improve local variability.

Jan 26, 2025 · To address reliability degradation caused by row hammer, the BCAT structure of DRAM cell should be investigated by varying key structural parameters related to D0 and D1 failures.

Abstract: Extensive reliability characterization of advanced DRAM (with and without HK/MG) with EUV process technology is presented. The technology features buried-channel array transistor(BCAT), dual-poly gate core/periphery transistors, 4-metal layers with Cu/Al interconnects, embedded DRAM capacitor, and with 8, 12, 16Gb chips, enabling ...

The characterization of data retention weak cells for 30 nm design rule DRAMs with BCAT and RCAT has been investigated. Most weak cells were classified as GIDL leaky cells in both cases. In the case of BCAT, the distance between the word line and the storage node, caused by the process distribution, is the main origin of weak cells.

This paper introduces an innovative process technology to realize a high-purity and low-resistance cell WL that can solve two critical hurdles simultaneously, enabling the DRAM node of 12 nm and beyond.