
2D and 2.5D Memory organization - GeeksforGeeks
Apr 3, 2025 · Simplicity: 2D memory organization is a simple and straightforward approach, with memory chips arranged in a two-dimensional grid. Cost-Effective: 2D memory organization is cost-effective, making it a popular choice for many low-power and low-cost devices.
Capacitorless Dynamic Random Access Memory with 2D …
Jan 10, 2025 · The fabricated 2T0C DRAM exhibits a rapid write speed of 20 ns, long data retention exceeding 1,000 s, and low energy consumption of approximately 0.2 fJ per write operation. Additionally, it demonstrates 3-bit storage capability and exceptional stability across numerous write/erase cycles.
Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM
Mar 24, 2025 · With 2D stacking, several layers with ‘planar’ DRAM memory arrays are stacked on top of each other. With 3D stacking, the transistors that make up the 2T0C bit cell are stacked and...
An in-memory computing architecture based on two-dimensional ...
Jun 7, 2021 · In this work, we propose a circuit architecture that integrates monolayer MoS 2 transistors in a two-transistor–one-capacitor (2T-1C) configuration. In this structure, the memory portion is similar...
Capacitorless Dynamic Random Access Memory with 2D …
Jan 21, 2025 · This method allows for the simultaneous fabrication of two damage-free MoS 2 transistors to form a capacitorless 2T0C DRAM cell, enhancing compatibility with 2D materials. The ultralow leakage current optimizes data retention and power efficiency.
2D planar DRAM architecture and 3D DRAM architectures
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future memory architectures to satisfy the ever-increasing demands on performance, power, and cost. This paper...
DRAM basics and its quest for thermal stability by optimizing ...
Feb 18, 2025 · To keep pace with the node-to-node improvement of the memory array, the DRAM periphery evolves accordingly in terms of area reduction and performance enhancement. In the longer term, more disruptive solutions may be envisioned that break the traditional ‘2D’ DRAM chip architecture.
In this work, we propose a 2T1C DRAM structure for in-memory computing. It integrates a monolayer graphene transistor, a monolayer MoS2 transistor, and a capacitor in a two-transistor-one-capacitor (2T1C) configuration.
Memory devices based on 2D materials for in‐memory computing.
In the case of in‐memory computing, logic operations are performed in situ within a memory unit, which mainly includes charge‐based memory (i.e., SRAM, DRAM, and Flash) and resistive switching...
2D‐material‐based DRAM, SRAM, and flash memory. a) Schematic ...
The discovery of two-dimensional (2D) van der Waals (vdW) materials brings vitality and possibilities to the microelectronics, optoelectronics, biopharmaceuticals, and chemical engineering.
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