Oct 20, 2021 · I have seen the abbreviation PHY beeing used for a handful of different things within the context of Ethernet: a PHY is a type of Ethernet physical layer (eg. 100BASE-TX, 10BASE-T) a PHY is an Ethernet transceiver IC (eg. an IC that converts 100BASE-TX to MII/RMII) a PHY is a physical layer device (more than just the transceiver IC)

A PHY chip or layer converts data between a "clean" clocked digital form which is only suitable for very-short-distance (i.e. inches) communication, and an analogue form which is suitable for longer range transmission. It has no particular clue as to what any of the bits "mean", nor how they should be interpreted or assembled.

Jul 11, 2018 · This specific datasheet doesn't specify what the value for the RSET resistor should be. But after a bit of looking around, I found another datasheet, page 8 for a Realtek IC (PHY) which uses a bandgap reference as well and they use a value of 2.49k for that resistor. The regulator voltages are about the same for both ICs (1.05V vs 1.0V).

Oct 5, 2020 · It's also very possible that only the PHY or the MAC offers a matched output impedance, in this case, the outputs on the unmatched device still needs to be source-terminated on one end. 3. Use the PHY delay option for RGMII clock signals. If the RGMII traces are length-matched, it should work with the default 2 ns delay..

Aug 14, 2022 · Generally, if I'm connecting a PHY to RJ45 connector, I would add center tap capacitors and Bob-Smith termination like below. But if I am connecting a PHY to another PHY, do I still need the Bob-Smith termination? Or can I just have center tap capacitors on both sides like below? Both PHYs share same GND but are powered by different rails.

Sep 1, 2010 · I'm trying to connect an RJ-45 jack with integrated magnetics (Belfuse L829-1X1T-91 datasheet) to an Ethernet PHY chip (Micrel KSZ8041TL datasheet). The TX+/-, RX+/-, and the LED pins are all easy enough to figure out, but I'm not sure what to do with the center taps (TCT and RCT) for the transformers.

Oct 17, 2019 · PHY's (Physical Interface IC's) and clocks can be confusing, there can be several clocks associated with one PHY. The PHY has an internal clock generated from it's oscillator (or external source with some PHY's). Some PHY's also provide an option to pipe out their clock, but are not essential to the MII interface.

Aug 10, 2023 · Using the existing UTMI+ specification as a starting point, the ULPI working group reduced the number of interface signals to 12 pins, with an optional implementation of 8 pins. The package size of PHY and Link IC’s are drastically reduced. This not only lowers the cost of Link and PHY IC’s, but also makes for a smaller PCB.

I have the choice of one of my PHY, but the other is embedded in an as-yet-unspecified PCIe to Ethernet IC (perhaps Gigabit but used in 100 Mbit/s mode), and it is critical that this PHY thinks there is a bona fide 100 Mbit/s Ethernet connection. I could use the following. simulate this circuit – Schematic created using CircuitLab

Jan 27, 2021 · It is recommended to consult your PHY vendor for the front end circuits they recommend for a particular application. IEEE 802.3cg requires all devices to tolerate (without damage) up to 60 V dc source limited to 2A across the medium-dependent interface (MDI) differential pair.