In semiconductor manufacturing, the 2 nm process is the next MOSFET (metal–oxide–semiconductor field-effect transistor) die shrink after the 3 nm process node.

2 days ago · In a rather unexpected turn of events, AMD announced late on Monday that it had obtained its first 2nm-class silicon, a core complex die (CCD) for its 6th Generation EPYC 'Venice' processor, which ...

Dec 11, 2023 · Samsung and Intel believe this is their best chance to close the game with TSMC. The world’s leading semiconductor companies are racing to make so-called “2 nanometer” processor chips that will...

TSMC 2nm (N2) technology development is on track and made good progress. N2 technology features the company’s first generation of nanosheet transistor technology with full-node strides in performance and power consumption.

Mar 25, 2025 · TL;DR: TSMC's 2nm process node is set for mass production in late 2025, with Apple as the first customer for its A20 Pro chip in the iPhone 18 Pro series in 2026. Initial 2nm wafers will arrive at ...

Apr 6, 2025 · These breakthroughs depend on shrinking chips to two nanometer (2nm) scale – so tiny it's measured in atoms. But behind the hype is a hidden battle over tools, trade wars, and the future of tech. The "nanometer" in chip manufacturing no longer refers to the actual size of transistors. Instead, it's a marketing term for the process technology ...

Feb 13, 2025 · TSMC's 2nm process, unveiled at IEDM 2025, sets a new benchmark in semiconductor technology with its nanosheet transistors, backside power delivery, and industry-leading density. While Intel and Samsung are closing the gap, TSMC's N2 offers superior performance and efficiency, making it a top choice for AI, mobile, and HPC applications.

Dec 14, 2024 · TSMC revealed additional details about its N2 (2nm-class) fabrication process at the IEEE International Electron Device Meeting (IEDM) earlier this month. The new production node promises a 24 to...

1 day ago · — Next-generation AMD EPYC CPU, codenamed “Venice,” is the first HPC product to be brought up on TSMC’s next-generation N2 node — SANTA CLARA, Calif., April 14, 2025 (GLOBE NEWSWIRE) -- AMD (NASDAQ: AMD) today announced its next-generation AMD EPYC™ processor, codenamed “Venice,” is the first HPC product in the industry to be taped …

A leading edge 2nm CMOS platform technology (N2) has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. This industry-leading N2 logic technology features energy-efficient gate-all-around nanosheet transistors, middle-of-line and backend-of-line interconnects with densest SRAM macro of ∼ 38.