Electronic Design1h
Broadcom Bets on 3.5D Packaging Technology to Build Bigger AI Chips
The tech integrates 2.5D packaging technology and 3D silicon stacking to usher in the next generation of “superchips” for AI.
Google’s new neural-net LLM architecture separates memory components to control exploding costs of capacity and compute
Titans architecture complements attention layers with neural memory modules that select bits of information worth saving in the long term.
Electronic Design6h
Maximize Flexibility in SoC Design with eFPGAs
An eFPGA is an FPGA that’s embedded into an ASIC to provide one or more programmable-logic fabrics for flexibility and ...
Semiconductor Engineering13h
Choosing The Right Memory Solution For AI Accelerators
The different flavors of DRAM each fill a particular AI niche.
Semiconductor Engineering1d
Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)
A new technical paper/mini-review titled “Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based ...
Imec spins out Vertical Compute memory chip firm in $20.5M deal
Europe's Imec.xpand is spinning out memory chip firm Vertical Compute in a seed investment round worth $20.5 million.
CNX Software3d
Seeed Studio XIAO Plus series adds more GPIOs through castellated holes
In response to community feedback for more I/O options, Seeed Studio has recently launched the Seeed Studio XIAO Plus series ...