If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix ...

Imagination Technology is primarily known for its GPU IP used by a wide range of companies across the industry, but in 2021 ...

The new “C3” variant has a single 160 MHz RISC-V core that out-performs the ESP8266, and at the same time includes most of the peripheral set of an ESP32. While RAM often ends up scarce on an ...

Third-gen Xiangshan may be close to performance of Arm’s made-for-HPC Neoverse 2 A key figure in in China’s drive to develop ...

RISC-V is a general-purpose license-free open Instruction Set Architecture ... and open source Instruction Set Simulator [ISS] like Spike as a reference model into their UVM environment and ...

The MIPS Coherence Manager and shared virtual memory (SVM) use an AMBA ACE interface to tie the RISC-V clusters and the I/O coherence unit (IOCU). The manager supports up to eight units, which usually ...

RISC-V is gaining attention throughout the semiconductor industry ... Having a custom instruction set simulator (ISS) is vital to success. Proper verification of a CPU design and associated ...

Ready for data centres China's Xiangshan project is set to deliver a high-performance RISC-V processor by 2025. The move will ...

A team from China's top government research academy pledged to produce this year a processor based on the open-source ...

Experts At The Table: What’s needed to be able to trust that a RISC-V implementation will work as expected across multiple designs using standard OSes. Semiconductor Engineering discussed the issue ...

The device features a “big” 800 x 480 pixel MIPI-DSI display, a 400 MHz ESP32-P4 dual-core microcontroller with 32MB of PSRAM ...

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, a leading developer of RISC-V chips and software for high-performance computing (HPC) and artificial intelligence (AI), today ...