A unique implementation of the classic Indian musical game Antakshari, built using RISC-V assembly language. This project demonstrates low-level programming concepts while preserving the fun of the ...

Frameworks like gem5, a microarchitecture-level simulator, support such investigations by providing ... their security mechanisms when integrated with low-power, open-source RISC-V processors. It will ...

If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix ...

A team from China's top government research academy pledged to produce this year a processor based on the open-source ...

Ready for data centres China's Xiangshan project is set to deliver a high-performance RISC-V processor by 2025. The move will ...

The MIPS Coherence Manager and shared virtual memory (SVM) use an AMBA ACE interface to tie the RISC-V clusters and the I/O coherence unit (IOCU). The manager supports up to eight units, which usually ...

A team from China’s top government research academy pledged to produce this year a processor based on the open-source chip-design architecture RISC-V, as Beijing advances its semiconductor self ...

From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan.

Imagination Technology is primarily known for its GPU IP used by a wide range of companies across the industry, but in 2021 ...

Third-gen Xiangshan may be close to performance of Arm’s made-for-HPC Neoverse 2 A key figure in in China’s drive to develop ...