Intel, TSMC, and Samsung are developing a broad set of technologies and relationships that will be required for the next generation of AI chips.

“TSMC also debuted new logic, specialty, advanced packaging, and 3D chip stacking technologies, each contributing to broad technology platforms in High Performance Computing (HPC ...

Cadence is expanding its design IP portfolio to meet the demands of the AI training market, delivering TSMC 9000-certified IP for 3D-IC design, including HBM3E 9.6G in N5/N4P and pre-silicon HBM3E ...

RedHawk-SC, RedHawk-SC Electrothermal, and Totem are certified for TSMC's advanced silicon process A16™ with Super Power Rail, a best-in-class backside power delivery solution for analog/block ...

In the 3D-IC space, Cadence offers a comprehensive chiplet design and packaging solution for TSMC’s 3DFabric. The company is expanding its IP portfolio for AI training applications with TSMC9000 ...

Also announce tool certification for TSMC N3C process and initial collaboration on TSMC’s newest A14 technology The Cadence Integrity ™ 3D-IC Platform now features enhanced support for ...

The Cadence EMX Planar 3D Solver is certified for TSMC’s N3 node and is undergoing N2P certification to meet advanced-node IC demands.

Cadence Design Systems, Inc. CDNS has announced an expansion of its long-standing collaboration with Taiwan Semiconductor Manufacturing Company (“TSMC”), aimed at accelerating time to silicon for ...