This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments. The PLL macro is implemented in Analog Bits’ proprietary architecture that ...

The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, 8Gbps and 16Gbps, and is designed to meet higher performance standards required for enterprise market applications. The PHY additionally ...