Design-Reuse11d
Sample CMOS latch-up design rules IP Listing
It is controlled by 0.9V (core) signals. ... The ODT-TVM-ULP-001C-40 is an ultra-low power temperature and voltage monitor designed in a standard 40nm CMOS process. The IP operates over the entire ...
Design-Reuse11d
Latch-up Improvement For Tap Less Library Through Modified Decoupling Capacitors Cells
The article proposes a layout for decoupling capacitors so as to improve the latch-up performance of the SoC. To understand the issue in completeness, one needs to understand the basic layout of a ...