The Lattice Double Data Rate (DDR3) Physical Interface (PHY) IP is a general-purpose IP that provides connectivity between a DDR3 memory Controller (MC) and the DDR3 memory devices compliant with ...

The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to ... DDR3/2 COMBO PHY CMD/ADDR BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process ...

The DDR3/4, LPDDR3/4 Combo IP, which integrates high-performance DDR PHY with a flexibly configurable controller, is a high-speed, low-power and small-area IP, providing customers with optimised ...