The DDR3 PHY IP provides the Industry standard DDR PHY Interface (DFI) bus at the local side to interface with the Memory Controller. The DFI protocol defines the signals, signal relationships, and ...

DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy. The combo PHY solution includes DDRn ...