For example, the uncertainty of when the DRAM will generate DQS relative to CK is +/- tDQSCK. For DDR2 400, this is +/- 500 ps, or 40% of the 2500 ps bit time. For DDR2 800, this is +/- 350ps, or 56% ...

A typical DDR2 memory controller is show in the block diagram in Figure 2. The PHY is responsible for the physical interface between the DDR DRAM and the rest of the system. Timing is controlled ...