With symmetric coherency, a Type-2 device can implement a Snoop Filter for HDM address ranges which allows it to map and manage larger amounts of memory more efficiently than before. In addition, ...

A new technical paper titled “Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices” was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. “The ...

“And it’s split across CXL (Compute Express Link), across ethernet, across PCIe Retimer class of products… we find ourselves in the position that we could be the Broadcom of this. So that ...

Rambus Compute Express Link (CXL) 2.0 Controller leverages a silicon-proven PCIe 5.0 controller architecture for the CXL.io path, and adds CXL.cache and CXL.mem paths specific to the CXL standard. The ...

XConn Technologies has unveiled its Apollo 2 hybrid switch, integrating both Compute Express Link (CXL) 3.1 and PCIe Gen 6.2 on a single chip. Designed to meet AI, machine learning, and ...